Heinz Nixdorf Institute: Dr.-Ing. Mario Porrmann

Mario Porrmann is senior lecturer in the System and Circuit Technology research group.

Address:
Heinz Nixdorf Institut
Universität Paderborn
Fürstenallee 11
33102 Paderborn

eMail:
porrmann(at)hni.upb.de
Telephone:
+49 5251 60-6352
Facsimile:
+49 5251 60-6351
Room:
F0.423

Short CV

Mario Porrmann is Acting Professor of the research group System and Circuit Technology at the Heinz Nixdorf Institute, University of Paderborn.

He graduated as “Diplom-Ingenieur” in Electrical Engineering at the University of Dortmund, Germany, in 1994. In 2001 he received a PhD in Electrical Engineering from the University of Paderborn, Germany for his work on performance evaluation of embedded neurocomputers. From 2001 to 2009 he was Assistant Professor (Akademischer Oberrat) in the research group “System and Circuit Technology” at the Heinz Nixdorf Institute, University of Paderborn.

His main scientific interests are in on-chip multiprocessor systems, dynamically reconfigurable computing and resource-efficient architectures for network components. Mario Porrmann has published more than 130 peer-reviewed papers in scientific journals as well as for international conferences. He is program committee member of several international conferences (e.g., FPL, ERSA, NAS) and serves regularly as a reviewer for a number of scientific conferences and journals (e.g., IEEE Transactions on Neural Networks, IEEE Transactions on Very Large Scale Integration Systems) as well as for research funding organizations. He is Associate Editor for ACM Transactions on Embedded Computing Systems, Special Issue on Configurable Computing, CAPA’09, and Program Vice Chair of the 5th IEEE International Conference on Networking, Architecture, and Storage, NAS 2010.

Publications: Books, Book Chapters and Journal Articles

Koester, M.; Luk, W.; Hagemeyer, J.; Porrmann, M.; Rueckert, U.:
Design Optimizations for Tiled Partially Reconfigurable Systems.
In: IEEE Transactions on Very Large Scale Integration Systems, accepted for publication.
Jungeblut, T.; Puttmann, C.; Dreesen, R.; Porrmann, M.; Thies, M.; Rückert, U.; Kastens, U.:
Resource Efficiency of Hardware Extensions of a 4-issue VLIW Processor for Elliptic Curve Cryptography.
In: Advances in Radio Science 2010, accepted for publication.
Purnaprajna, M.; Porrmann, M.; Rueckert, U.; Hussmann, M.; Thies, M.; Kastens, U.:
Run-Time Reconfiguration of Multiprocessors Based on Compile-Time Analysis.
In: ACM Transactions on Reconfigurable Technology and Systems (TRETS), accepted for publication.
Pohl, P.; Paiz, C.; Porrmann, M.:
vMAGIC - Automatic Code Generation for VHDL.
In: International Journal of Reconfigurable Computing, Hindawi Publishing Corporation, Volume 2009, Article ID 205149.
Purnaprajna, M., Porrmann, M., and Rueckert, U.:
Run-time Reconfigurability in Embedded Multiprocessors.
In: SIGARCH Computer Architecture News, Volume 37, Number 2, pp. 30–37, July 2009.
Adelt, P.; Donoth, J.; Gausemeier, J.; Geisler, J.; Henkler, S.; Kahl, S.; Klöpper, B.; Krupp, A.; Münch, E.; Oberthür, S.; Paiz, C.; Podlogar, H.; Porrmann, M.; Radkowski, R.; Romaus, C.; Schmidt, A.; Schulz, B.; Vöcking, H.; Witkowski, U.; Witting, K.; Znamenshchykov, O.:
Selbstoptimierende Systeme des Maschinenbaus – Definitionen, Anwendungen, Konzepte.
HNI-Verlagsschriftenreihe, 2008, Band 234.
El-Darawy, M.; Pfau, T.; Hoffmann, S.; Peveling, R.; Wördehoff, C.; Koch, B.; Porrmann, M.; Adamczyk, O.; Noe, R.:
Fast Adaptive Polarization and PDL Tracking in a Realtime FPGA Based Coherent PolDM-QPSK Receiver.
In IEEE Photonics Technology Letters, Volume 20, Issue 21, pp. 1796–1798, November 1, 2008.
Hoffmann, S.; Bhandare, S.; Pfau, T.; Adamczyk, O.; Wordehoff, C.; Peveling, R.; Porrmann, M.; Noe, R.:
Frequency and Phase Estimation for Coherent QPSK Transmission With Unlocked DFB Lasers.
In IEEE Photonics Technology Letters, Volume 20, Issue 18, pp. 1569–1571, September 15, 2008.
Puttmann, C., Shokrollahi, J., Porrmann, M., and Rückert, U.:
Hardware Accelerators for Elliptic Curve Cryptography.
In Advances in Radio Science, Vol. 6, pp. 259–264, 2008.
Jungeblut, T., Grünewald, M., Porrmann, M., and Rückert, U.:
Realtime multiprocessor for mobile ad hoc networks.
In Advances in Radio Science, Vol. 6, pp. 239–243, 2008.
Pfau, T.; Hoffmann, S.; Adamczyk, O.; Peveling, R.; Herath, V.; Porrmann, M.; Noé, R.:
Coherent optical communication: Towards realtime systems at 40 Gbit/s and beyond.
In Optics Express, Vol. 16, Issue 2, pp. 866-872, January, 2008.
Paiz, C.; Pohl, C.; Porrmann, M.:
Hardware-in-the-Loop Simulations for FPGA-Based Digital Control Design.
In Juan Andrade-Cetto, Jean-Louis Ferrier, Jos´e Miguel Costa dias Pereira, Joaquim Filipe (Editors) Informatics in Control, Automation and Robotics, Vol. 3, pp. 355-372, Springer-Verlag, 2008.
Koester, M.; Kalte, H.; Porrmann, M.; Rückert, U.:
Defragmentation Algorithms for Partially Reconfigurable Hardware.
In VLSI-SoC: From Systems to Silicon. IFIP International Federation for Information Processing, Vol. 240, pp. 41-53, Springer, Boston, USA, 2007.
Niemann, J.-C.; Puttmann, C.; Porrmann, M.; Rückert, U.:
Resource efficiency of the GigaNetIC chip multiprocessor architecture.
In Journal of Systems Architecture (JSA), special issue on Architectural premises for pervasive computing, Vol. 53, Issues 5-6, pp. 285-299, May-June 2007.
Pfau, T.; Hoffmann, S.; Peveling, R.; Bhandare, S.; Ibrahim, K.; Adamczyk, O.; Porrmann, M.; Noé, R.; Achiam, Y.:
First Real-Time Data Recovery for Synchronous QPSK Transmission with Standard DFB Lasers.
IEEE Photonics Technology Letters, vol. 18(18), pp. 1907-1909, September 2006.
Pfau, T.; Hoffmann, S.; Peveling, R.; Ibrahim, S.; Adamczyk, O.; Porrmann, M.; Bhandare, S.; Noé, R.; Achiam; Y.:
Synchronous QPSK Transmission at 1.6 Gbit/s with Standard DFB Lasers and Real-time Digital Receiver.
In IEE Electronic Letters, Volume 42, Number 20, pp. 1175-1176, September 2006.
Porrmann, M.; Witkowski, U.; Rückert, U.:
Implementation of Self-Organizing Feature Maps in Reconfigurable Hardware.
In Omondi, Amos; Rajapakse, Jagath (Editors) FPGA Implementations of Neural Networks Springer-Verlag, Chapter 9, pp. 253-276, 2005.
Grünewald, M.; Niemann, J.; Porrmann, M.; Rückert, U.:
A framework for design space exploration of resource efficient network processing on multiprocessor SoCs.
In Crowely, Patrick; Franklin, Mark A.; Hadimioglu, Haldun; Onufryk, Peter Z. (Editors) Network Processor Design: Issues and Practices Morgan Kaufmann Publishers, vol.3, Chapter 12, pp. 245-277, 2005.
Kalte, H.; Kettelhoit, B.; Köster, M.; Porrmann, M.; Rückert, U.:
A System Approach for Partially Reconfigurable Architectures.
In International Journal of Embedded Systems (IJES), Inderscience Publisher, Vol. 1, pp. 274-290, 2005.
Porrmann, M.; Witkowski, U. Rückert, U.:
A Massively Parallel Architecture for Self-Organizing Feature Maps.
IEEE Transactions on Neural Networks, Special Issue on Hardware Implementations, 14(5): pp. 1110-1121, Sep., 2003.
Porrmann, M.:
Leistungsbewertung eingebetteter Neurocomputersysteme.
Dissertation, Universität Paderborn, Heinz Nixdorf Institut, Schaltungstechnik, HNI-Verlagsschriftenreihe, Paderborn, Band 104, 2002.
Rüping, S.; Porrmann, M.; Rückert, U.:
SOM Accelerator System.
Neurocomputing, 21: pp. 31-50, 1998.

Publications at International Conferences

2010

Puttmann, C.; Porrmann, M.; Grassi, P. R.; Santambrogio, M.; Rückert, U.:
High Level Specification of Embedded Listeners for Monitoring of Network-on-Chips.
In: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France, 2010, accepted for publication.

2009

Herath, V.; Peveling, R.; Pfau, T.; Adamczyk, O.; Hoffmann, S.; Wördehoff, C.; Porrmann, M.; Noé, R.:
Chipset for a Coherent Polarization-Multiplexed QPSK Receiver.
In Proceedings of OFC/NFOEC 2009, San Diego, California, USA, March 22-26, 2009.
Pfau, T.; Peveling, R.; Herath, V.; Hoffmann, S.; Wördehoff, C.; Adamczyk, O.; Porrmann, M.; Noé, R.:
Towards Real-Time Implementation of Coherent Optical Communication.
In Proceedings of OFC/NFOEC 2009, San Diego, California, USA, March 22-26, 2009, invited paper.
Köster, M.; Luk, W.; Hagemeyer, J.; Porrmann, M.:
Design Optimizations to Improve Placeability of Partial Reconfiguration Modules.
In Proceedings of DATE: Design, Automation and Test in Europe, Nice, France, April 20-24, 2009.
Grassi, P. R.; Pohl, C.; Porrmann, M.:
Reconfiguration Viewer
Design, Automation and Test in Europe DATE, University Booth, Nice, France, April 20-24, 2009.
Pohl, C.; Fuest, R.; Porrmann, M.:
Manageable Dynamic Reconfiguration with EVE - Extendable VHDL Editor
Design, Automation and Test in Europe DATE, University Booth, Nice, France, April 20-24, 2009.
Grassi, P. R.; Santambrogio, M. D.; Puttmann, C.; Pohl, C.; Porrmann, M.:
A High Level Methodology for Monitoring Network-on-Chips.
Diagnostic Services in Network-on-Chips (DSNOC’09), Workshop at Design, Automation and Test in Europe DATE, Nice, France, April 24, 2009.
Porrmann, M.; Hagemeyer, J.; Romoth, J.; Strugholtz, M.:
Rapid Prototyping of Next-Generation Multiprocessor SoCs.
In Proceedings of Semiconductor Conference Dresden, SCD 2009, Dresden, Germany, April 29-30, 2009, invited paper.
Liß, C.; Porrmann, M.; Rückert, U.:
Early Exploration of Network Processor Architectures Using Cadence InCyte Chip Estimator.
CDNLive, EMEA2009, Munich, Germany, May 18-20, 2009 (best paper award).
Liß, C.; Porrmann, M.; Rückert, U.:
InCyte ChipEstimator in Research and Education.
CDNLive, EMEA2009, Munich, Germany, May 18-20, 2009.
Porrmann, M.; Purnaprajna, M.: Puttmann, C.:
Self-optimization of MPSoCs Targeting Resource Efficiency and Fault Tolerance.
NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2009), San Francisco, California, USA, July 29 – August 1, 2009, invited paper.
Grassi, P. R.; Santambrogio, M. D.; Hagemeyer, J.; Pohl, C.; Porrmann, M.:
SiLLis: A Simplified Language for Monitoring and Debugging of Reconfigurable Systems.
In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '09), Las Vegas, USA, pp. 174–180, July 13-16, 2009.
Purnaprajna, M.; Pohl, C.; Porrmann, M.; Rückert, U.:
Using Run-time Reconfiguration for Energy Savings in Parallel Data Processing.
In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '09), Las Vegas, USA, pp. 119–125, July 13-16, 2009.
Porrmann, M.; Hagemeyer, J.; Pohl, C.; Romoth, J.; Strugholtz, M.:
RAPTOR – A Scalable Platform for Rapid Prototyping and FPGA-based Cluster Computing.
In Proceedings of the Int. Conf. on Parallel Computing, ParCo2009, Symposium on Parallel Computing with FPGAs, September 2009, Lyon, France.
Dreesen, R.; Jungeblut, T.; Thies, M.; Porrmann, M.; Rückert, U.; Kastens, U.
A Synchronization Method for Register Traces of Pipelined Processors.
In Proceedings of the International Embedded Systems Symposium 2009 (IESS '09), Schloss Langenargen, Germany, September 14-16, , pp. 207–217, 2009.
Paiz, C.; Hagemeyer, J.; Pohl, C.; Porrmann, M.; Rückert, U.; Schulz, B.; Peters, W.; Böcker, J.
FPGA-Based Realization of Self-Optimizing Drive-Controllers.
In Proceedings of the 35th Annual Conference of the IEEE Industrial Electronics Society (IECON 2009), pp. 2868–2873, Porto, Portugal, November 3-5, 2009.
Paiz, C.; Pohl, C.; Radkowski, R.; Hagemeyer, J.; Porrmann, M.:
FPGA-in-the-Loop-Simulations for Dynamically Reconfigurable Applications.
In Proc. of the 2009 Int. Conf. on Field-Programmable Technology (FPT'09), pp. 372–375, Sydney, Australia, December 9-11, 2009.
Pohl, C.; Hagemeyer, J.; Romoth, J.; Porrmann, M.; Rückert, U.:
Using a Reconfigurable Compute Cluster for the Acceleration of Neural Networks.
In Proc. of the 2009 Int. Conf. on Field-Programmable Technology (FPT'09), pp. 368–371, Sydney, Australia, December 9-11, 2009.

2008

Hagemeyer, J.; Köster, M.; Porrmann, M.:
Hardware Virtualization Exploiting Dynamically Reconfigurable Architectures.
In 1. GI/ITG KuVS Fachgespräch Virtualisierung, Paderborn, Germany, pp. 19–28, February 11–12, 2008.
Münch, E.; Gambuzza, A.; Paiz, C.; Pohl, C.; Porrmann, M.:
FPGA-in-the-Loop Simulations with CAMEL-View.
In Self-optimizing Mechatronic Systems: Design the Future, 7th International Heinz Nixdorf Symposium, Paderborn, Germany, pp. 429–445, February 20-21, 2008.
Pfau, T.; Wördehoff, C.; Peveling, R.; Ibrahim, S. K.; Hoffmann, S.; Adamczyk, O.; Bhandare, S.; Porrmann, M.; Noé, R.; Koslovsky, A.; Achiam, Y.; Schlieder, D.; Grossard, N.; Hauden, J.; Porte, H.:
Ultra-Fast Adaptive Digital Polarization Control in a Realtime Coherent Polarization-Multiplexed QPSK Receiver.
In Proceedings of OFC/NFOEC 2008, San Diego, California, USA, February 24-28, 2008.
Purnaprajna, M.; Puttmann, C.; Porrmann, M.:
Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography.
In Proceedings of DATE: Design, Automation and Test in Europe, Munich, Germany, pp. 1462–1467, March 10-14, 2008.
Pohl, C.; Paiz, C.; Porrmann, M.:
A Hardware-in-the-Loop Design Environment for FPGAs.
In Design, Automation and Test in Europe DATE, University Booth, Munich, Germany, March 10-14, 2008.
Jungeblut, T.; Dreesen, R.; Porrmann, M.; Rückert, U.; Hachmann, U.:
Design Space Exploration for Resource Efficient VLIW-processors.
In Design, Automation and Test in Europe DATE, University Booth, Munich, Germany, March 10-14, 2008.
Puttmann, C.; Shokrollahi, J.; Porrmann, M.:
Resource Efficiency of Instruction Set Extensions for Elliptic Curve Cryptography.
In Proceedings of the 5th International Conference on Information Technology: New Generations, ITNG 2008, Las Vegas, Nevada, USA, pp. 131-136, April 7-9, 2008.
Griese, B.; Brinkmann, A.; Porrmann, M.:
SelfS – A Real-Time Protocol for Virtual Ring Topologies.
In Proceedings of the 16th International Workshop on Parallel and Distributed Real-Time Systems (WPDRTS'08), (on CD), Miami, Florida, USA, April 14, 2008.
Purnaprajna, M.; Porrmann, M.:
Run-time Reconfigurable Multiprocessors.
In Proceedings of the 22nd International Parallel and Distributed Processing Symposium (IPDPS 2008), PhD Forum, Miami, Florida, USA, April, 2008.
Pohl, C.; Paiz, C.; Porrmann, M.:
vMAGIC – VHDL Manipulation and Automation for Reliable System Development.
In 3rd International Workshop on Reconfigurable Computing Education, (on CD), April 10, 2008, Montpellier, France.
Hoffmann, S.; Pfau, T.; Adamczyk, O.; Wördehoff, C.; Peveling, R.; Porrmann, M.; Noé, R.; Bhandare, S.:
Frequency Estimation and Compensation for Coherent QPSK Transmission with DFB Lasers.
In Proc. OSA Topical Meeting Coherent Optical Technologies and Applications (COTA), July 13-16, 2008, CWB4, Boston, MA, USA.
Pfau, T.; El-Darawy, M.; Wördehoff, C.; Peveling, R.; Hoffmann, S.; Koch, B.; Adamczyk, O.; Porrmann, M.; Noé, R.:
32-krad/s Polarization and 3-dB PDL Tracking in a Realtime Digital Coherent Polarization-Multiplexed QPSK Receiver.
In Proceedings of the 2008 IEEE/LEOS Summer Topical Meetings, Acapulco, Mexico, pp. 105–106, July 21–23.
Noé, R.; Hoffmann, S.; Pfau, T.; Adamczyk, O.; Herath, V.; Peveling, R.; Porrmann, M.:
Realtime Digital Polarization and Carrier Recovery in a Polarization-Multiplexed Optical QPSK Transmission.
In Proc. IEEE/LEOS Summer Topical Meetings 2008, pp. 99–100, July 21-23, 2008, Acapulco, Mexico, (invited paper).
El-Darawy, M.; Pfau, T.; Wördehoff, C.; Koch, B.; Hoffmann, S.; Peveling, R.; Porrmann, M.; Noé, R.:
Realtime 40 krad/s Polarization Tracking with 6 dB PDL in Digital Synchronous Polarization-Multiplexed QPSK Receiver.
In Proceedings of ECOC 2008, Brussels, Belgium, September 21-25, 2008.
Purnaprajna, M.; Porrmann, M.:
Run-time Reconfigurable Cluster of Processors.
In Proceedings of 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), Workshop on Design, Architecture and Simulation of Chip Multi-Processors, IEEE Computer Society, November 8-12, 2008, Lake Como, Italy.

2007

Niemann, J.-C.; Liss, C.; Porrmann, M.; Rückert, U.:
A multiprocessor cache for massively parallel SoC architectures.
In Proceedings of ARCS'07: Architecture of Computing Systems, pp. 83-97, Zurich, Switzerland, March 12-15, 2007.
Pohl, C.; Paiz, C.; Porrmann, M.:
Hardware-in-the-Loop Entwicklungsumgebung für informationsverarbeitende Komponenten mechatronischer Systeme.
In 5. Paderborner Workshop Entwurf mechatronischer Systeme, pp. 69-79, March 22-23, 2007.
Rana, V.; Santambrogio, M.; Sciuto, D.; Kettelhoit, B.; Koester, M; Porrmann, M.; Rückert, U.:
Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux.
In Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS2007) - Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, Long Beach, California, USA, March 26 - 27, (on CD) 2007.
Hagemeyer, J.; Kettelhoit, B.; Koester, M.; Porrmann, M.:
INDRA - Integrated Design Flow for Reconfigurable Architectures.
In Design, Automation and Test in Europe DATE, University Booth, on CD, Nice, France, April 16-20, 2007.
Jungeblut, T.; Grünewald, M.; Porrmann, M.; Rückert, U.:
Real-Time Multiprocessor SoC for Mobile Ad Hoc Networks.
In Design, Automation and Test in Europe DATE, University Booth, on CD, Nice, France, April 16-20, 2007.
Paiz, C.; Kettelhoit, B.; Porrmann, M.:
A design framework for FPGA-based dynamically reconfigurable digital controllers.
In Proceedings of the IEEE International Symposium on Circuits and Systems ISCAS2007, pp. 3708-3711, New Orleans, USA, May 27-30, 2007.
Paiz, C.; Porrmann M.:
The Utilization of Reconfigurable Hardware to Implement Digital Controllers: A Review.
In Proceedings of the IEEE International Symposium on Industrial Electronics, pp. 2380-2385, Vigo, Spain, June 4-7, 2007.
Noe, R.; Pfau, T.; Adamczyk, O.; Peveling, R.; Herath, V.; Hoffmann, S.; Porrmann, M.; Ibrahim, S. K.; Bhandare, S.:
Real-time Digital Carrier & Data Recovery for a Synchronous Optical Quadrature Phase Shift Keying Transmission.
In Proceedings of System Microwave Symposium, 2007. IEEE/MTT-S International, Honolulu, HI, USA, pp. 1503 - 1506, June 3-8, 2007 (invited paper).
Hagemeyer, J.; Kettelhoit, B.; Koester, M.; Porrmann, M.:
Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs.
In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '07), Las Vegas, USA, June 25-28, 2007 (Distinguished Paper).
Pfau, T.; Peveling, R.; Hoffmann, S.; Bhandare, S.; Ibrahim, S.; Sandel, D.; Adamczyk, O.; Porrmann, M.; Noé, R.; Achiam, Y.; Schlieder, D.; Koslovsky, A.; Benarush, Y.; Hauden, J.; Grossard, N.; Porte, H.:
PDL-Tolerant Real-time Polarization-Multiplexed QPSK Transmission with Digital Coherent Polarization Diversity Receiver.
In Proceedings of the 2007 IEEE/LEOS Summer Topical Meetings, pp. 17-18, Portland, USA, July 23-25, 2007.
Pfau, T.; Adamczyk, O.; Herath, V.; Peveling, R.; Hoffmann, S.; Porrmann, M.; Noe, R.:
Realtime Optical Synchronous QPSK Transmission with DFB lasers.
In Proceedings of the 2007 IEEE/LEOS Summer Topical Meetings, pp. 15-16, Portland, USA, July 23-25, 2007.
Porrmann, M.
A Layer-Model Based Methodology for the Design of Dynamically Reconfigurable Systems.
Invited Talk at the 2nd Int. Conf. On Industrial and Information Systems (ICIIS 2007), Reconfigurable Computing Workshop, Peradeniya, Sri Lanka, August, 8-11, 2007.
Porrmann, M.
Flexible Hardware Platforms for Dynamic Reconfiguration.
Invited Talk at the 2nd Int. Conf. on Industrial and Information Systems (ICIIS 2007), Reconfigurable Computing Workshop, Peradeniya, Sri Lanka, August, 8-11, 2007.
Hagemeyer, J.; Kettelhoit, B.; Koester, M.; Porrmann, M.:
A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAs.
In Proceedings of the 17th International Conference on Field Programmable Logic and ist Applications (FPL 2007), pp. 331-338, Amsterdam, Netherlands, August 27-29, 2007.
Puttmann, C.; Niemann, J.-C.; Porrmann, M.; Rückert, U.:
GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors.
In Proceedings of the 10th EUROMICRO Conference on Digital System Design, pp. 495-502, Luebeck, Germany, August 27-31, 2007.
Schulz, B.; Paiz, C.; Hagemeyer, J.; Mathapati, S.; Porrmann, M.; Böcker, J.:
Run-Time Reconfiguration of FPGA-Based Drive Controllers.
In Proceedings of the 12th European Conference on Power Electronics and Applications (on CD), Aalborg, Denmark, September 2-5, 2007.
Pfau, T.; Peveling, R.; Samson, F.; Romoth, J.; Hoffmann, S.; Bhandare, S.; Ibrahim, S.; Sandel, D.; Adamczyk, O.; Porrmann, M.; Noé, R.; Hauden, J.; Grossard, N.; Porte, H.; Schlieder, D.; Koslovsky, A.; Benarush, Y.; Achiam, Y.:
Polarization-Multiplexed 2.8 Gbit/s Synchronous QPSK Transmission with Real-Time Digital Polarization Tracking
In Proceedings of ECOC 2007, Vol.3, pp.263-264, Berlin, September 16-20, 2007.
Hußmann, M.; Thies, M.; Kastens, U.; Purnaprajna, M.; Porrmann, M; Rückert, U.:
Compiler-Driven Reconfiguration of Multiprocessors.
In Workshop on Application Specific Processors (WASP), held in conjunction with CODES+ISSS, pp. 3-10, Salzburg, Austria, October 4, 2007..

2006

Porrmann, M.; Niemann, J.-C.:
Teaching Reconfigurable Computing - Theory and Practice
In Proc. of the 1st International Workshop on Reconfigurable Computing Education, on CD, Karlsruhe, Germany, March 1, 2006.
Sauer, C.; Gries, M.; Dirk, S.; Niemann, J.-C.; Porrmann, M.; Rückert, U.:
A Lightweight NoC for the NOVA Packet Processing Platform.
In Design, Automation and Test in Europe DATE, Future Interconnect and Network-on-Chip (NoC) Workshop, on CD, Munich, Germany, March 6-10, 2006.
Niemann, J.-C.; Puttmann, C.; Porrmann, M.; Rückert, U.:
GigaNetIC - A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications.
In ARCS'06 Architecture of Computing Systems, pp. 268-282, March13-16, 2006 (best paper award).
Hagemeyer, J.; Kettelhoit, B.; Porrmann, M.:
Dedicated Module Access in Dynamically Reconfigurable Systems.
In Proceedings of the 20th IEEE International Parallel and Distributed Processing Symposium, on CD, Rhodes Island, Greece, April 25-29, 2006.
Kalte, H.; Porrmann, M.:
REPLICA2Pro: Task Relocation by Bitstream Manipulation in VIRTEX-II/Pro FPGAs
. In Proceedings of the 3rd Conference on Computing Frontiers, pp. 403-412, Ischia, Italy, May 03 - 05, 2006.
Jäger, B.; Porrmann, M.; Rückert, U.:
Bio-Inspired Massively Parallel Architectures for Nanotechnologies.
In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2006), pp. 1961 - 1964, Island of Kos, Greece, May 21 - 24, 2006.
Hoffmann, S.; Pfau, T.; Adamczyk, O.; Peveling, R.; Porrmann, M.; Noé, R.:
Hardware-Efficient and Phase Noise Tolerant Digital Synchronous QPSK Receiver Concept.
In Coherent Optical Technologies and Applications (COTA 2006), on CD, OSA, Whistler, BC, Canada, June 28-30, 2006.
Koester, M.; Kalte H.; Porrmann M.:
Relocation and Defragmentation for Heterogeneous Reconfigurable Systems.
In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '06), CSREA Press, pp. 70-76, Las Vegas, USA, June 27-30, 2006.
Hoffmann, S.; Pfau, T.; Peveling, R.; Bhandare, S.; Adamczyk, O.; Porrmann M.; Noé, R.:
Synchrone 1,6-Gbit/s-QPSK-Datenübertragung in Echtzeit mit DFB-Lasern.
In Workshop der ITG Fachgruppe 5.3.1, Modellierung photonischer Komponenten und Systeme, pp. 21-27, Nürnberg, Germany, July 17-18, 2006.
Griese, B.; Porrmann, M.:
A Reconfigurable Ethernet Switch for Self-Optimizing Communication Systems.
In Proceedings of the IFIP Conference on Biologically Inspired Cooperative Computing (BICC 2006), pp. 115-124, Santiago de Chile, Chile, August 20-25, 2006.
Kettelhoit, B.; Porrmann, M.:
A Layer Model for Systematically Designing Dynamically Reconfigurable Systems.
In Proceedings of the 16th International Conference on Field Programmable Logic and Applications, pp. 547-552, Madrid, Spain, August, 28-30, 2006.
Paiz, C.; Pohl, C.; Porrmann, M.:
Reconfigurable Hardware in-the-Loop Simulations for Digital Control Design.
In 3rd International Conference on Informatics in Control, Automation and Robotics (ICINCO), pp. 39-46, Setubal, Portugal, August 2006.
Griese, B.; Kettelhoit, B.; Porrmann, M.:
Evaluation of on-chip interfaces for dynamically reconfigurable coprocessors.
In Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering, pp. 214-219, Bialystok, Poland, September 13-17, 2006.
Sauer, C.; Gries, M.; Niemann, J.; Porrmann, M.; Thies, M.:
Application-driven Development of Concurrent Packet Processing Platforms.
In 5th International Symposium on Parallel Computing in Electrical Engineering, pp. 55-61, Bialystok, Poland, September 13-17, 2006.
Pfau, T.; Hoffmann, S.; Peveling, R.; Bhandare, S.; Adamczyk, O.; Porrmann, M.; Noé, R.; Achiam, Y.:
1.6 Gbit/s Real-Time Synchronous QPSK Transmission with Standard DFB Lasers.
In Proc. 32nd European Conference on Optical Communication (ECOC 2006), Cannes, France, September 24-28, 2006.
Paiz, C.; Chinapirom, T.; Witkowski U.; Porrmann, M.:
Dynamically Reconfigurable Hardware for Autonomous Mini-Robots.
In 32nd Annual Conference of the IEEE Industrial Electronics Society (IECON-2006), pp. 3981-3986, Paris, France, November 2006.

2005

Kettelhoit, B.; Kalte, H.; Porrmann, M.; Rückert, U.:
Dynamically Reconfigurable Hardware for Self-Optimizing Mechatronic Systems.
In 5. GMM/ITG/GI-Workshop Multi-Nature Systems, pp. 97-101, Dresden, Germany, February 2005.
Kettelhoit, B.; Klassen, A.; Paiz, C.; Porrmann, M.; Rückert, U.:
Rekonfigurierbare Hardware zur Regelung mechatronischer Systeme.
In 3. Paderborner Workshop: Intelligente mechatronische Systeme, pp. 195-205, Paderborn, Germany, March 30-31, 2005.
Köster, M.; Porrmann, M.; Rückert, U.:
Placement-Oriented Modeling of Partially Reconfigurable Architectures.
In Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005)-Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, on CD, Denver, Colorado, USA, April 4 - 5, 2005.
Kalte, H.; Gareth, L.; Porrmann, M.; Rückert, U.:
REPLICA: A bitstream manipulator filter for module relocation in partial reconfigurable systems.
In Proceedings of the 19th International Parallel and Distributed Processing Symposium, Reconfigurable Architectures Workshop, IEEE Computer Society, on CD, Denver, Colorado, USA, April 4 - 5, 2005.
Niemann, J.; Porrmann, M.; Rückert, U.:
A Scalable Parallel SoC Architecture for Network Processors.
In IEEE Computer Society Annual Symposium on VLSI 2005 (ISVLSI 2005), IEEE Computer Society Press, pp. 311-313, May 11-12 2005.
Niemann, J.; Porrmann, M.; Sauer, C.; Rückert, U.:
An Evaluation of the Scalable GigaNetIC Architecture for Access Networks.
In Advanced Networking and Communications Hardware Workshop (ANCHOR), held in conjunction with the ISCA 2005, on CD, Madison, Wisconsin, USA, June 4-8, 2005.
Paiz, C.; Kettelhoit, B.; Klassen, A.; Porrmann, M.; Rückert, U.:
Dynamically Reconfigurable Hardware for Digital Controllers in Mechatronic Systems.
In IEEE International Conference on Mechatronics (ICM2005), pp. 675-680, Taipei, Taiwan, July 2005.
Eickhoff, R.; Niemann, J.; Porrmann, M.; Rückert, U.:
Adaptable Switch boxes as on-chip routing nodes for networks-on-chip.
In From Specification to Embedded Systems Application, International Embedded Systems Symposium (IESS), A. Rettberg , M. C. Zanella and F. J. Rammig Ed., pp. 201-210, Manaus, Brazil, August 15-17 2005.
Griese, B.; Oberthür, S.; Porrmann, M.:
Component case study of a self-optimizing RCOS/RTOS system: A reconfigurable network service.
In From Specification to Embedded Systems Application, International Embedded Systems Symposium (IESS), A. Rettberg , M. C. Zanella and F. J. Rammig Ed., pp. 267-277, Manaos, Brazil, August 15-17 2005.
Kalte, H.; Porrmann, M.:
Context Saving and Restoring for Multitasking in Reconfigurable Systems.
In 15th International Conference on Field Programmable Logic and Applications, pp. 223-228, Tampere, Finland, 24-28 August 2005.
Köster, M.; Kalte, H.; Porrmann, M.:
Run-Time Defragmentation for Partially Reconfigurable Systems.
In Proceedings of the International Conference on Very Large Scale Integration of System-on-Chip (IFIP VLSI-SoC), pp. 109-115, Perth, Australia, October 17-19 2005.
Liß, C.; Peveling, R.; Porrmann, M.; Rückert, U.:
Technologieplanung in der Mikroelektronik - von Moore’s Law zur Nanotechnologie-Roadmap.
In Symposium für Vorausschau und Technologieplanung, pp. 87-103, Berlin, Germany, Nov. 9-10, 2005.
Köster, M.; Kalte, H.; Porrmann, M.:
Task Placement for Heterogeneous Reconfigurable Architectures.
In Proceedings of the IEEE 2005 Conference on Field-Programmable Technology (FPT'05), pp. 43-50, Singapore, December 11-14 2005.

2004

Grünewald, M.; Niemann, J.-C.; Porrmann, M.; Rückert, U.:
A framework for design space exploration of resource efficient network processing on multiprocessor SoCs.
In Proceedings of the 3rd Workshop on Network Processors & Applications, pp. 87-101, Madrid, Spain, February 14-15 2004.
Grünewald, M.; Niemann, J.-C.; Porrmann, M.; Rückert, U.:
A mapping strategy for resource-efficient network processing on multiprocessor SoCs.
In Proceedings of DATE: Design, Automation and Test in Europe, CNIT La Défense, pp. 758-763, Paris, France, February 16-20 2004.
Kalte, H.; Porrmann, M.; Rückert, U.:
Leistungsbewertung unterschiedlicher Einbettungsvarianten dynamisch rekonfigurierbarer Hardware.
In Workshop Proceedings: ARCS 2004 - Organic and Pervasive Computing, GI-Edition Lecture Notes in Informatics (LNI, pp. 235-244), Augsburg, March 26 2004.
Kalte, H.; Porrmann, M.; Rückert, U.:
System-on-Programmable-Chip Approach Enabling Online Fine-Grained 1D-Placement.
In 11th Reconfigurable Architectures Workshop (RAW 2004), on CD, Santa Fé, New Mexico, USA, April 26-27 2004.
Kalte, H.; Köster, M; Kettelhoit, B; Porrmann, M; Rückert, U:
A Comparative Study on System Approaches for Partially Reconfigurable Architectures.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA04), pp. 70-76, Las Vegas, Nevada, USA, June 21-24 2004.
Griese, B.; Vonnahme, E.; Porrmann, M.; Rückert, U.:
Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC Architectures.
In Proceedings of the 14th International Conference on Field Programmable Logic and its Applications (FPL2004), pp. 842-846, Antwerp, Belgium, 30 August - 1 September 2004.
Franzmeier, M.; Pohl, C.; Porrmann, M.; Rückert, U.:
Hardware Accelerated Data Analysis.
In Proceedings for the 4th International Conference on Parallel Computing in Electrical Engineering (PARALEC 2004), pp. 309-314, Dresden, Germany, September 7-10 2004.
Grünewald, M.; Kastens, U.; Le, D. K.; Niemann, J.-C.; Porrmann, M.; Rückert, U.; Thies, M.; Slowik, A.:
Network Application Driven Instruction Set Extensions for Embedded Processing Clusters.
In Proceedings of PARELEC 2004, International Conference on Parallel Computing in Electrical Engineering, pp. 209-214, Dresden, Germany, September 7-10 2004.
Vonnahme, E.; Griese, B.; Porrmann, M.; Rückert, U.:
Dynamic reconfiguration of real-time network interfaces.
In Proceedings of the 4th International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), pp. 376-379, Dresden, Germany, September 7-10 2004.
Vonnahme, E.; Griese, B.; Porrmann, M.; Rückert, U.:
Dynamische Rekonfiguration echtzeitfähiger Netzwerkschnittstellen.
In Proceedings VDE Kongress 2004 - ITG Fachtagung Ambient Intelligence, VDE Verlag, Band 1, pp. 99-104, Berlin, Germany, October 18-20, 2004.
Niemann, J.-C.; Porrmann, M.; Rückert, U.:
Parallele Architekturen für Netzwerkprozessoren.
In Proceedings VDE Kongress 2004 - ITG Fachtagung Ambient Intelligence, VDE Verlag, Berlin, Volume 1, pp. 105-110, October 18-20 2004.
Pohl, C.; Franzmeier, M.; Porrmann, M.; Rückert, U.:
gNBX - Reconfigurable Hardware Acceleration of Self-Organizing Maps.
In Proceedings of the IEEE International Conference on Field Programmable Technology (FPT'04). Brisbane, Australia, December 6-8 2004.
Kalte, H.; Porrmann, M.; Rückert, U.:
Study on Column Wise Design Compaction for Reconfigurable Systems.
In Proceedings of the IEEE International Conference on Field Programmable Technology (FPT'04). Brisbane, Australia, December 6-8 2004.
Hagen, G.; Niemann, J.-C.; Porrmann, M.; Sauer, C.; Slowik, A.; Thies, M.:
Developing an IP-DSLAM Benchmark for Network Processor Units.
In ANCHOR 2004, Advanced Networking and Communications Hardware Workshop, held in conjunction with the 31st Annual International Symposium on Computer Architecture (ISCA 2004), Munich, Germany, 2004.

2003

Bonorden, Olaf; Brüls, Nikolaus; Le, Dinh Khoi; Kastens, U.; Meyer auf der Heide, Friedhelm; Niemann, Jörg-Christian; Porrmann, Mario; Rückert, Ulrich; Slowik, Adrian; Thies, Michael:
A holistic methodology for network processor design.
In Proceedings of the Workshop on High-Speed Local Networks held in conjunction with the 28th Annual IEEE Conference on Local Computer Networks (LCN2003), pp. 583-592, 20. - 24. Okt., 2003.

2002

Brinkmann, André; Niemann, Jörg-Christian; Hehemann, Ingo; Langen, Dominik; Porrmann, Mario; Rückert, Ulrich:
On-Chip Interconnects for Next Generation System-on-Chips.
In Proc. of the 15th Annual IEEE International ASIC/SOC Conference, pp. 212-215, Rochester, NY, USA, 25. - 28. Sep., 2002.
Kalte, Heiko; Porrmann, Mario; Rückert, Ulrich:
A Prototyping Platform for Dynamically Reconfigurable System on Chip Designs.
In Proceedings of the IEEE Workshop Heterogeneous reconfigurable Systems on Chip (SoC), Hamburg, Germany, 2002.
Langen, Dominik; Niemann, Jörg-Christian; Porrmann, Mario; Kalte, Heiko; Rückert, Ulrich:
Implementation of a RISC Processor Core for SoC Designs - FPGA Prototype vs. ASIC Implementation.
In Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC), Hamburg, Germany, 2002.
Porrmann, Mario; Franzmeier, Marc; Kalte, Heiko; Witkowski, Ulf; Rückert, Ulrich:
A reconfigurable SOM hardware accelerator.
In Proceedings of the 10th European Symposium on Artificial Neural Networks, ESANN'2002, pp. 337-342, Bruges, Belgium, Apr., 2002.
Porrmann, Mario; Witkowski, Ulf; Kalte, Heiko; Rückert, Ulrich:
Dynamically Reconfigurable Hardware - A New Perspective for Neural Network Implementations.
In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL2002), pp. 1048-1057, Montpellier, France, 2002.
Porrmann, Mario; Witkowski, Ulf; Kalte, Heiko; Rückert, Ulrich:
Implementation of Artificial Neural Networks on a Reconfigurable Hardware Accelerator.
In Proceedings of the 10th Euromicro Workshop on Parallel, Distributed and Network-based Processing (PDP 2002), pp. 243-250, Gran Canaria Island, Spain, Jan., 2002.

2001

Niemann, Jörg-Christian; Witkowski, Ulf; Porrmann, Mario; Rückert, Ulrich:
Extension Module for Application-Specific Hardware on the Minirobot Khepera.
In Autonomous Minirobots for Research and Edutainment (AMiRE 2001), pp. 279-288, Paderborn, Germany, 22. - 24. Okt., 2001.
Porrmann, Mario; Rückert, Ulrich; Landmann, Jörg; Marks, Karl Michael:
XipChip - A Multiprocessor CPU for Multifunction Peripherals.
In Proceedings of The 5th World Multi-Conference on Systemics, Cybernetics and Informatics (SCI), Band 15, pp. 512-517, Orlando, Florida, USA, Jul., 2001.
Porrmann, Mario; Rüping, Stefan; Rückert, Ulrich:
The Impact of Communication on Hardware Accelerators for Neural Networks.
In Proceedings of The 5th World Multi-Conference on Systemics, Cybernetics and Informatics (SCI), Band 3, pp. 248-253, Orlando, Florida, USA, Jul., 2001.
Porrmann, Mario; Kalte, Heiko; Witkowski, Ulf; Niemann, Jörg-Christian; Rückert, Ulrich:
A Dynamically Reconfigurable Hardware Accelerator for Self-Organizing Feature Maps.
In Proceedings of The 5th World Multi-Conference on Systemics, Cybernetics and Informatics, SCI 2001, Band 3, pp. 242-247, Orlando, Florida, USA, Jul., 2001.

2000

Kalte, Heiko; Porrmann, Mario; Rückert, Ulrich:
Using a Dynamically Reconfigurable System to Accelerate Octree Based 3D Graphics.
In Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA2000), Band 5, pp. 2819-2824, Monte Carlo Resort, Las Vegas, Nevada, USA, 2000.
Kalte, Heiko; Porrmann, Mario; Rückert, Ulrich:
Rapid Prototyping System für dynamisch rekonfigurierbare Hardwarestrukturen.
In Workshop: Architekturentwurf und Entwicklung eingebetteter Systeme (AES2000), pp. 149-157, Karlsruhe, Germany, 2000.

1999

Porrmann, Mario; Rüping, Stefan; Rückert, Ulrich:
SOM Hardware with Acceleration Module for Graphical Representation of the Learning Process.
In Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy, and Bio-Inspired Systems (MicroNeuro99), pp. 380-386, Granada, Spain, 7. - 9. Apr., 1999.

1998

Porrmann, Mario; Heittmann, Arne; Rüping, Stefan; Rückert, Ulrich:
A Hybrid Knowledge Processing System.
In Proceedings of the Conference Neural Networks and their Applications (NEURAP), pp. 177 - 184, Marseille, France, 11. - 13. Mrz., 1998.

1997

Porrmann, Mario; Landmann, Jörg; Marks, Karl Michael; Rückert, Ulrich:
HIBRIC-MEM, a Memory Controller for PowerPC Based Systems.
In Proceedings of the 23rd EUROMICRO Conference, pp. 653-663, Budapest, Ungarn, 1. - 4. Sep., 1997.
Rüping, Stefan; Porrmann, Mario; Rückert, Ulrich:
SOM Hardware-Accelerator.
In Workshop on Self-Organizing Maps (WSOM), Nr.1997, pp. 136-141, Espoo, Finnland, 4. - 6. Jun., 1997.
Rüping, Stefan; Porrmann, Mario; Rückert, Ulrich:
A High Performance SOFM Hardware-System.
In Proceedings of the International Work-Conference on Artificial and Natural Neural Networks (IWANN97), pp. 772-781, Lanzarote, Spain, 4. - 6. Jun., 1997.

1996

Palm, Günther; Rückert, Ulrich; Porrmann, Mario; Schwenker, Friedhelm: Neuronale Assoziativspeicher.
In Neuroinformatik Statusseminar, pp. 419-432, Apr., 1996.