The  Cadence academic network was launched in 2007 by Cadence Europe. The aim was to promote the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence. A knowledge network among selected European universities, research institutes, industry advisors and Cadence was established to facilitate the sharing of technology expertise in the areas of verification, design and implementation of microelectronic systems.

Cadence tools are used during various labs to give a practical understanding of the modern design flows used for the development of microelectronic devices.

The lecture  Semiconductor Circuit Technology covers the design flow highly-integrated microelectronic devices and systems. In the labs the students have to dimension and design full custom standard cells using Cadence Design Framework II.

In the lecture  Design of Microelectronic Systems the students are taught the digital designflow starting from an abstract hardware description up to a final ASIC implementation. Various Cadence tool (e.g. RTL Compiler, SoC Encounter, Encounter Power System) are used in the labs to explain the intermediate design steps.

The lecture Management of SoC Design Processes and Products the students learn how to plan SoC systems on high level as well as on medium level, which enables them to think outside the box and to keep management objectives in mind when doing engineering decisions. The Cadence InCyte ChipEstimator XL is used to plan System-on-Chips with low effort, but high accuracy.

The project Management of SoC Design Processes and Products is a more hands-on version of the lecture Management of SoC Design Processes and Products. Students use Cadence InCyte ChipEstimator XL to investigate, e.g., correlations between power consumption and chip package cost.

The lecture Case Studies of Management of Electronic Products and Product Development deals with an in-depth examination of a fictional commercial product development in form of a case study, which is based on real examples. Case studies that involved SoC development are enriched with real system properties from Cadence InCyte Chip Estimator XL.

Cadence Tools are generally used in many projects at the System and Circuit Technology Group. For the ASIC design of processor architectures we use a  highly automated design flow based on Cadence tools:

• Realtime Multiprocessor SoC:
  • 8-Core multiprocessor for Mobile Ad-Hoc networks
  • 180nm UMC standard cell technology
  • 25 mm² Core area, ~15 Million transistors
  • 2.1 MBit on-chip memory
  • 300mW @ 100MHz
• CoreVA VLIW architecture
  • 4-issue VLIW processor
  • 65nm LP STMicroelectronics standard cell technology
  • 2.6mm² core area (incl. 256 kBit on-chip memory)
  • <100mW @ 400MHz
• CoreVA Ultra-Low-Power RISC processor (under development)
  • 32-bit RISC processor
  • Custom 65nm sub-threshold standard cell technology
  • 0.4mm² core area
  • Dynamic voltage/frequency scaling (DVFS)
  • ~0.010mW @ 1 MHz and 400mV (preliminary)
  • Cadence CPF implementation flow